Reduced scheduling delays with automated post-routing verification of SerDes high-speed serial links

Most high-speed serial links are not verified after routing is complete because the process is time-consuming and skill-intensive – and SI experts are rare. As a result, most serial channels are laid out according to rules, checked by manual inspection, and released to manufacturing without in-depth analysis. Unverified channels can lead to lengthy (and hectic) prototype debugging, board rotations, and planning delays.

What is needed is an automated post-routing verification process that checks all channels of a design for detailed compliance with a SerDes protocol standard. Such a solution allows designers to catch issues early in the layout process when they’re easier to fix, and release designs to manufacturing with confidence knowing that all of their serial channels have been verified.

The problem: lengthy post-road simulations and prototype debugging

If post-routing verification of serial links is so important, why are so many PCB designs sent to prototype manufacturing without full verification? Part of the problem is the prevalence of serial links in modern products. Everything is full of serial links today – computers, phones, smartwatches, cars – and the list goes on. There are lots of designs, and lots of links to check out. This brings us to the second, larger problem: there simply aren’t enough signal integrity experts to handle that much work. Signal integrity experts are often like artists – everyone has their own style and approaches the task a little differently. Much of what they do is based on detailed knowledge and experience, and that’s individual. There really is no such thing as a signal integrity analysis assembly line – the analysis streams are not standardized and therefore not scalable. It’s like anything else with a limited, highly skilled workforce – too much work and too few people able to do the art.

The result: Companies must decide which sections of which designs deserve expert time and attention. These projects benefit from the assistance of experts, the others must do without or wait for an expert to be available. Even on a single PCB layout, this can create costly bottlenecks. Companies cannot afford the resulting delays. Yet they can’t afford to let random errors pass undetected in prototypes in the lab, where finding, isolating, and debugging signal integrity issues takes longer, costs more, and is notoriously difficult. So what to do?

Until now, PCB design teams have generally followed one of four paths to analyze their designs after layout.

  1. Send the card for crafting and hope for the best. The theory is that if the manufacturer’s guidelines were followed, the design should work. However, how can one be sure that all design guidelines have been followed?
  2. Visually inspect the layout to ensure design guidelines and best practices have been followed. It’s definitely better than option 1, but visual inspection is tedious and time-consuming, making it very error-prone. Design errors can be found this way, but it’s always a hit-and-miss proposition.
  3. Submit the design to an in-house signal integrity expert for analysis. There are two requirements here: (a) there must be an in-house signal integrity expert, and (b) the expert must have the time and tools available. Since there are too many designs and too few experts to go around, this is usually not the case. Yet even when an expert is available and their analysis shows issues that need to be fixed, the updated layout has to come back to the end of the queue, causing further delays.
  4. Send the layout to an external signal integrity consultant. This is a way to bypass an internal scan queue or run a scan when no internal expert exists. This will likely grab attention faster, but any design changes will cost both time and money, as the consultants won’t be running this second set of simulations for free.

None of these options are particularly attractive. Either they are taking too many risks in order to get design to manufacturing sooner, or they are imposing long lead times in order to perform a detailed signal integrity analysis. What’s needed is a fast and reliable way to validate designs after layout, without having to wait for a signal integrity expert or outside consultant.

The solution: automated post-delivery verification

There are three essential steps to validate serial links before sending a design to manufacturing:

  1. Electromagnetic modeling
  2. Analysis
  3. Results processing

These three flows have traditionally been largely manual efforts, consisting of multiple steps and requiring IS experts. If we combine the three steps into a process diagram for a traditional flow, it looks like what is shown in Figure 1.

Fig. 1: Process diagram for a traditional compliance analysis flow.

Red arrows indicate parts of the flow where data should be reviewed for accuracy and parts of the process repeated if things need to be adjusted. Again, this diagram shows a compliance analysis flow using a traditional methodology. An IBIS-AMI flow would have fewer elements, but the simulation step itself would be more complex.

Siemens DISW’s HyperLynx makes it possible to validate all serial links in a design for protocol compliance before sending the board to manufacturing, without a time-consuming, highly skilled, and labor-intensive process.

HyperLynx can automate the entire post-layout verification process because Siemens provides all the necessary EDA tools in the HyperLynx family, integrated into a single, automated workflow. This includes automated identification of critical areas that need to be modeled with a full-wave solver, assembly of the complete channel model from individual parts once everything has been solved, analysis of the resulting channel models for compliance (analysis) and formatting the results to show which channels passed, which channels failed and by how many (results processing). The HyperLynx process for post-route serial channel protocol verification resembles what is shown in Figure 2.

Fig. 2: HyperLynx process for post-route serial channel protocol verification.

This automated process means that all channels of a large system design can be modeled and analyzed. The electromagnetic modeling process can be accelerated by running multiple solvers in parallel, so users can control execution time against trade-offs between required resources based on their project needs. More importantly, HyperLynx tells you exactly what you want to know: which channels are passing, which channels are failing, and by how much — all in a detailed report that includes frequency and time domain plots and eye diagrams.

Everything you need to know, in one place, organized and referenced. This means you can analyze all channels in your design for protocol compliance – automatically, overnight. It’s pretty quick and easy to scan your channels for issues while the design is still being laid out. So you don’t have to wait for the layout to be finished and the touch-ups to be more expensive.

Fig. 3: Detailed HyperLynx reports.

For a more detailed look at why full post-route analysis is considered too time-consuming and expensive and how the automated compliance analysis workflow using HyperLynx overcomes the limitations of these traditional post-route analysis methods, please download the white paper Automated Compliance Analysis from Serial Links Reduce Planning Risk. The document explains how design teams can verify all serial links in their designs overnight, improving design performance and reducing schedule risk, and helping you get high-speed designs today of tomorrow.

Todd Westerhof

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Todd Westerhoff is a product marketing manager for high-speed system design in Siemens EDA’s Electronic Board Systems Division. Westerhoff has over 43 years of experience in modeling and simulating electronic systems, including 26 years of signal integrity experience. Westerhoff was heavily involved in the IBIS-AMI modeling specification when it was created. Prior to joining Siemens EDA, he held technical and management positions at SiSoft, Cisco and Cadence. He has also worked as an independent signal integrity consultant, developing analysis methodologies for major systems and integrated circuit manufacturers. Westerhoff holds a BEEE degree from Stevens Institute of Technology in Hoboken, NJ