NSITEXE Selects ImperasDV for Functional Design Verification of Automotive-Grade RISC-V Processor – EEJournal

Imperas RISC-V reference model, test suites and verification IPs for advanced CPU verification by “lock step comparison”, including asynchronous events and coverage analysis.

Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced that NSITEXE, Inc., a DENSO Corporation company that develops and sells high-performance IP semiconductors for automotive applications, has selected ImperasDV™ for advanced RISC-V processor hardware design verification. This expands and expands the use of Imperas simulation technology, models, verification IP and tools from NSITEXE for the next generation of 64-bit RISC V-based designs including vector accelerators for automotive AI applications ( artificial intelligence) with verification leading to the level required to achieve ISO 26262 ASIL D.

RISC-V is an open ISA (Instruction Set Architecture) standard that allows processor developers to optimize configuration with standard extensions and custom instructions. The recently ratified RISC-V vector extensions support the computational requirements of hardware accelerators for applications involving linear algebra, which is well suited for emerging AI algorithms and workloads in advanced automotive applications.

ImperasDV is the integrated solution for RISC-V processor verification that provides an adaptable framework based on the open standard RVVI (RISC-V Verification Interface) which supports basic RTL verification with the Imperas reference model in a “lock-step-compare” methodology in addition to test suites and other verification IPs. ImperasDV covers verification tasks for implementations ranging from basic controllers to advanced designs including vector extensions, privileged mode security protections, multi-hart and custom extensions. Additionally, the freedom of RISC-V’s ISA open standard enables advanced processor technology in many new application areas, with developers exploring techniques such as superscalar, out-of-order execution, multithreading, multicore heterogeneous and processor bays. as well as other new and creative approaches for the next generation of domain-specific devices. ImperasDV completes verification tasks for development teams at the forefront of processor exploration.

“The flexibility of RISC-V ISA coupled with the performance of vector extensions is an ideal starting point for AI accelerators for automotive applications,” said Hideki Sugimoto, CTO of NSITEXE, Inc., a DENSO Corporation group company. “To meet the verification requirement for our next generation of processors, we have developed an optimized verification flow with ImperasDV which our design team has put together with detailed configuration options to deliver their comprehensive verification plans that deliver the cutting-edge quality our customers expect.

“RISC-V’s open ISA enables a new wave of processor design innovation across the spectrum of compute requirements in nearly every market segment,” said Nobuyuki Ueyama, Chairman of eSOL TRINITY Co., Ltd.. “High quality CPU verification is not a simple task, but the ease of use and configurable approach with RVVI offered by ImperasDV allows the eSOL TRINITY team to support expert design teams to NSITEX and other major RISC-V users in Japan.

“RISC-V’s ISA open standard enables a fundamental shift in processor development, with developers able to explore and innovate solutions with optimized solutions for targeted applications,” said Simon Davidmann, CEO of Imperas Software Ltd. “RISC-V’s flexibility on the design side has a direct impact on the verification task, and since value-added features are at the heart of development, we developed ImperasDV be adaptable to all implementations to allow our customers and users to independently verify state-of-the-art designs. NSITEXE is a pioneer in the development of advanced RISC-V vector accelerators for AI, and we are excited to see Imperas technology and ImperasDV meeting the quality requirements of automotive applications.

is available now, with more details available at Imperas.com/ImperasDV.

the ImperasDV RISC-V processor verification technology is already actively used by many high profile customers, some of whom have working silicon prototypes and are currently working on 2nd generation designs. These customers, partners and users cover all RISC-V users, from open source to commercial; from research to industry; high performance computing microcontrollers. A select sample of these includes – Codasip, EM Microelectronics (Sample), NSITEX (denso), Nvidia Network (Mellanox), OpenHW Group, MIPS technology, Seagate Technology, Silicon Laboratoriesand Valtrix systemsas well as many others that have not yet been made public.

The open standard RVVI (RISC-V Verification Interface) provides the essential guidelines for the infrastructure around the processor testbed that supports the growing verification IP ecosystem for RISC-V processor verification. New RVVI open standard and methodology, is based on an open specification (https://github.com/riscv-verification/RVVI) and can be adapted to any configuration allowed in the RISC-V specifications. By adopting the RVVI standard, developers can take advantage of all common out-of-the-box components and explore additional options with reusable verification IP across projects.

Free riscvOVPsimMore The package, including the Imperas RISC-V reference model, sample test suites, and statement coverage analysis, including updates to the latest RISC-V ratified specifications, is also available on OVPworld at address www.ovpworld.org/riscvOVPsimPlus.

RISC-V Days Tokyo 2022 Spring
Mr. Shuzo Tanaka, eSOL TRINITY Co., Ltd. will be presenting the Imperas Platinum RISC-V Verification Talk at RISC-V Days Tokyo 2022 Spring, May 31-June 2, 2022.

High quality RISC-V verification with new open standards RVVI and ImperasDV
Abstract: RISC-V extends design freedoms for SoC developers with optimized processors. This speech describes RVVI (RISC-V Verification Interface), an open standard interface for RISC-V processor verification with efficiency, reusability and flexibility. Highlights will cover test examples of some popular open source IP cores and tips for new CPU DV projects.
Speaker: Shuzo Tanaka, eSOL TRINITY Co., Ltd.
Co-author: Simon Davidmann – Imperas Software Ltd
Co-author: Lee Moore – Imperas Software Ltd
When: May 31, 2022 at 4:30 p.m. JST (GMT+9)
Or: Tokyo, Japan.

For more information and registration, please visit https://riscv.or.jp/en/risc-v-days-tokyo-2022-spring-fr/

eSOL TRINITY (TRINITY) is a leading solution provider for the design and development of embedded software. TRINITY’s complete solution consists of consulting and professional services, tools and the promotion of engineering experts. With its rich experience in the automotive market and its wide range of expertise, including cybersecurity, functional safety, process development and the software and hardware development environment for RISC-V, TRINITY contributes to the improvement software quality and reduced development costs for the customer. TRINITY was established in 2015 as a wholly owned subsidiary of eSOL Co., Ltd., the leading provider of real-time in-vehicle software solutions. For more information on eSOL TRINITY, please visit https://www.esol-trinity.co.jp/

About Imperas
Imperas is the leading provider of RISC-V processor models, hardware design verification solutions, and virtual prototypes for software simulation. Imperas, together with Open Virtual Platforms (OVP), promotes the availability of open source models for a range of processors, IP vendors, CPU architectures, system IPs and platform models. reference of processors and systems ranging from simple single-core bare metal platforms to full heterogeneous multis. -basic systems booting SMP Linux. All models are available from Imperas at www.imperas.com and the Open Virtual Platforms (OVP) website.