Imperas Software, a developer of RISC-V simulation solutions, has announced the official version 1.0 of the RVVI (RISC-V Verification Interface) as the basis of the new RISC-V verification ecosystem.
RISC-V’s open Instruction Set Architecture (ISA) standard has sparked interest in optimized processors in many different market segments and application areas.
Previously, SoC developers were constrained to only be able to consider a few limited mainstream IP cores. The design freedom of RISC-V has therefore generated considerable interest in innovation.
This design freedom also shifts the responsibility for verification from a few IP providers to any adopters who choose to exploit these new design freedoms associated with RISC-V.
Successful adoption of processors has previously focused on software (such as development tools, compilers, and operating systems) and hardware (EDA tools for RTL simulation, gate-level synthesis, and physical layout) and while all ISAs have many unique and special features, these dual ecosystems of hardware and software have been able to support them all. However, since the IP cores of previous processors all came from a single source, the verification task tended to be done in-house with techniques tightly guarded as trade secrets.
Additionally, since “known” CPU IP was the baseline assumption for all SoC verification streams, CPU IP cores were not tested by SoC adopters. Now, with RISC-V, as an open ISA standard, any developer can explore the full range of design features offered by the ISA specification. This means that any adopters who choose to extend, modify, or create a custom processor core will also need to meet Design Verification (DV) requirements.
Imperas recently announced the ImperasDV solution with a combination of quality reference model, test suites and verification methodology to address the full spectrum of RISC-V implementations.
The device under test (DUT) RTL is typically configured with a test bench to control and monitor operational analysis during the verification process. The testbench should support all kernel functionality, including specialized DV tasks for testing and analysis with debugging operations. As the test bench interfaces with the RTL processor (DUT), test generators, reference model, verification IP and EDA tools for RTL simulation, any errors or admissions have a significant impact on the quality of the test and could allow errors to escape. unnoticed in late design stages, silicon prototypes or even production devices.
Although a custom testbed can be created for any target DUT, this approach limits reuse options and leverages other components that could save time and effort.
The new open standard and RVVI methodology is based on an open specification and can be adapted to any configuration allowed in the RISC-V specifications.
By adopting the RVVI standard, developers will be able to take advantage of all common out-of-the-box components and explore additional options with third-party verification IP. Additionally, since many projects evolve into further enhancements for subsequent designs, the investment in verification infrastructure can be reused for both future core projects and ongoing regression frameworks.
RVVI Technical Summary
The new open standard RVVI (RISC-V Verification Interface) provides:
- Seamless integration between RTL, reference model and testbench
- Direct-coupled integration for accurate lock-step-and-compare instruction
- Supports multi-hart, superscalar, and out-of-service CPU pipelines
- Fully UVM Compliant
- SystemVerilog integration compatible with tools and environments offered by Cadence, Siemens EDA, Synopsys and Metrics cloud-based tools.
- The new RVVI (RISC-V Verification Interface) is an open standard developed by Imperas with advice and support from customers and core users, is available now and is being adopted by the testing and RISC-V verification.
“We are at the epicenter of the largest verification liability migration in history of IP and EDA tools from processors,” said Simon Davidmann, CEO of Imperas Software. “Now every SoC design team can adopt the processor design flexibility of RISC-V for optimized domain-specific solutions – but this marks the end of the ‘one size fits all’ era of processor IP. Expanding the scope of established SoC verification flows to accommodate the added complexity of the RISC-V DV processor defines the new verification ecosystem, which is unique for RISC-V ISA adopters.