Imperas unifies new RISC-V verification ecosystem with RVVI – EEJournal

New open standard RISC-V Verification Interface (RVVI) provides adaptability and reuse of verification IP for the growing community of developers performing CPU verification

Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced the official version 1.0 of the new RVVI (RISC-V Verification Interface) as the basis of the new RISC-V verification ecosystem. RISC-V’s open Instruction Set Architecture (ISA) standard has spurred interest in optimized processors in nearly every market segment and application area. Since previously, SoC developers were constrained to consider only a few limited mainstream IP cores, RISC-V’s design freedom has sparked tremendous interest in innovation. This design freedom also shifts the responsibility for verification from a few IP providers to any adopters who choose to exploit these new design freedoms of RISC-V.

Key ecosystems for successful adoption of mass-market processors previously focused on software (such as development tools, compilers, and operating systems) and hardware (EDA tools for RTL simulation, autism synthesis, door level and physical layout). Although all ISAs have many unique and special features, these two hardware and software ecosystems have supported them all. However, since the IP cores of previous processors all came from a single source, the verification task was done in-house with techniques closely guarded as trade secrets. Additionally, since “known” CPU IP was the baseline assumption for all SoC verification streams, CPU IP cores were not tested by SoC adopters. Now, with RISC-V, as an open ISA standard, any developer can explore the full range of design features offered by the ISA specification. So, in turn, any adopters who choose to extend, modify, or build a custom CPU core will also need to meet Design Verification (DV) requirements.

Imperas recently announced the ImperasDV solution with a combination of quality reference model, test suites and verification methodology to address the full spectrum of RISC-V implementations. The device under test (DUT) RTL is typically configured with a test bench to control and monitor operational analysis during the verification process. The testbench should support all kernel functionality, including specialized DV tasks for testing and analysis with debugging operations. As the test bench interfaces with the RTL processor (DUT), test generators, reference model, verification IP and EDA tools for RTL simulation, any errors or admissions have a significant impact on the test quality and could allow errors to escape. unnoticed in late design stages, silicon prototypes or even production devices. Although a custom testbed can be created for any target DUT, this approach limits reuse options and leverages other components that could save time and effort. New RVVI open standard and methodology, is based on an open specification (see this link on GitHub) and can be adapted to any configuration allowed in the RISC-V specifications. By adopting the RVVI standard, developers can take advantage of all common out-of-the-box components and explore additional options with third-party verification IP. Additionally, since many projects evolve into further enhancements for subsequent designs, the investment in verification infrastructure can be reused for both future core projects and ongoing regression frameworks.

RVVI Technical Summary and Highlights
– New open standard RVVI (RISC-V Verification Interface) provides:
* Seamless integration between RTL, reference model and testbench
* Direct-coupled integration for precise lock-and-match instruction
* Supports multi-hart, superscalar and off-duty CPU pipelines
* Fully UVM Compliant
* SystemVerilog integration compatible with tools and environments offered by Cadence, Siemens EDA, Synopsys and Metrics cloud-based tools.

New RVVI (RISC-V Verification Interface) is an open standard developed by Imperas with advice and support from major customers and users, is available now and is being adopted by the RISC-V testing and verification community: https https://github.com/riscv-verification/RVVI.

“The contributors to the OpenHW Verification Working Group are pioneers in advancing the quality of open source hardware IP ready for mainstream adoption – quality deliverables are the hallmark of any hardware IP vendor. trusted, commercial or open source,” said Rick O’Connor, President and CEO of OpenHW Group. “Growth in OpenHW memberships over the past three years significantly expands the roadmap for IP-based projects, with projects addressing the needs of application-class devices supporting Linux, embedded security, and compute-intensive applications. with personalized instructions. the RVVI An open and flexible standard methodology greatly assists members and contributors of the OpenHW Verification Working Group with efficient and quality verification for the full range of CORE-V IP projects.

“We are at the epicenter of the largest verification liability migration in history of IP and EDA tools from processors,” said Simon Davidmann, CEO of Imperas Software Ltd. “Now every SoC design team can adopt the processor design flexibility of RISC-V for optimized domain-specific solutions – but this marks the end of the ‘one size fits all’ era of processor IP. Expanding the scope of established SoC verification flows to accommodate the added complexity of the RISC-V DV processor defines the new verification ecosystem, which is unique for RISC-V ISA adopters.

Availablity
the RVVI (RISC-V Verification Interface) is available at https://github.com/riscv-verification/RVVI.

the ImperasDV RISC-V processor verification technology is already actively used by many high profile customers, some of whom have working silicon prototypes and are currently working on 2nd generation designs. These customers, partners and users cover all RISC-V users, from open source to commercial; from research to industry; high performance computing microcontrollers. A select sample of these includes – Codasip, EM Microelectronics (Sample), NSITEX (denso), Nvidia Network (Mellanox), OpenHW Group, MIPS technology, Seagate Technology, Silicon Laboratoriesand Valtrix systemsas well as many others that have not yet been made public.

ImperasDV is available now, more details are available at Imperas.com/ImperasDV.

Free riscvOVPsimMore The package, including the Imperas RISC-V reference model, test suites and instruction coverage analysis, including updates to the latest RISC-V ratified specifications, is also available on OVPworld at www.ovpworld.org/riscvOVPsimPlus.

DVCon 2022
Imperas will host an in-depth technical tutorial on RVVI as part of ‘Introduction to the 5 Levels of RISC-V Processor Verification‘ at DVCon 2022, in addition to discussions and presentation on the latest trends and developments for RISC-V verification. More details on the tutorial, discussions and to request a demo are available at this link.

About Imperas
Imperas is the leading provider of RISC-V processor models, hardware design verification solutions, and virtual prototypes for software simulation. Imperas, with Open Virtual Platforms (OVP), promotes the availability of open source models for a range of processors, IP vendors, CPU architectures, system IPs and reference platform models from processors and systems ranging from simple single-core bare metal platforms to full heterogeneous multi-platforms. -basic systems booting SMP Linux. All models are available from Imperas at www.imperas.com and the Open Virtual Platforms (OVP) website.
For more information about Imperas, please visit www.imperas.com. Follow Imperas on LinkedIn, Twitter @ImperasSoftware and YouTube.