IC Verification Tool Tackles the Blurred Lines Between Analog and Digital

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Siemens EDA has unveiled a new mixed-signal verification tool that chip designers can use to evaluate system-on-chips (SoCs) used everywhere, from data centers and 5G networks to cars and IoT devices.

Symphony Pro, as Siemens describes it, is a cutting-edge platform that aims to disrupt the status quo in mixed-signal verification, delivering up to 10x productivity gains. The tool includes a comprehensive and intuitive visual debugging cockpit that promises to make it much easier for chipmakers to find and fix bugs in mixed-signal designs, which are some of the most complex and challenging parts of chips. fast.

Symphony Pro is an advanced level of its Symphony platform, which when launched in 2018 promised up to 5x faster acceleration than existing solutions. It has been a success, with over 100 customers using the Electronic Design Automation (EDA) tool to register around 80 chips to date.

What sets Symphony Pro, which is based on the company’s Analog Fast SPICE (AFS) technology, apart is that it leverages more robust and automated digital verification technologies to increase the productivity of chip engineers.

Sumit Vishwakarma, senior product manager for Siemens’ mixed-signal unit, said that with Symphony Pro, he’s trying to keep up with chipmakers who are rapidly pushing the boundaries of mixed-signal architectures, resulting in inevitably additional complexity for chipmakers.

As a result, bugs are increasingly slipping through their fingers, derailing chip design and increasing time to market. In this environment, companies need faster, more accurate, and easy-to-use software that can verify the connectivity, functionality, and performance of mixed-signal circuits.

Blur the boundaries

Siemens EDA hopes to turn heads with Symphony Pro as engineers integrate more advanced analog IP into their chip designs. According to IBS Research, approximately 85% of all chip design startups are now mixed-signal.

“We keep hearing that we live in a digital world,” Vishwakarma said. “But the world around us is analog. And so what we really live in is a mixed-signal world where digital and analog work together.”

Analog IP is increasingly ubiquitous in modern chips, whether integrating the analog signal chain with digital signal processors in 5G massive MIMO radios or RF sampling data converters. digital in radar. There are also switch chips that transmit data to processors in the data center via high-speed SerDes. Additionally, chipmakers are deploying network chips for factories with Ethernet PHY inside.

The technology is set to become even more important as AMD and Intel enter the chip age, cutting chips into smaller modular building blocks that are then packaged into a larger package.

“The concept behind a chiplet is divide and conquer,” Vishwakarma noted. And since even the most advanced chips in the world struggle to stay on track with Moore’s Law, “we started thinking outside the box.”

When you break down a larger processor into chiplets, you need to ensure that they can talk to each other almost as fast as they could sharing the same die. To do this, companies use SerDes, which is the cornerstone of high-speed serial interconnects, ranging from the PCIe standard to NVIDIA’s NvLink, and the UCIe die-to-die chiplet standard supported by Arm, Google, Intel, Microsoft, TSMC, and others.

“Where there is a chiplet, there is a mixed signal,” Vishwakarma said.

Play catch-up

With the blurring lines between analog and digital in modern chips, companies are looking for tools that can meet the challenge, Vishwakarma said.

Verification of mixed signals is a difficult task because before you can test that everything works on the chip, you have to run simulations on the analog and digital parts of the design. But using a single verification platform to model both digital and analog domains is a tall order.

“In the digital realm, there are a lot of innovations with new digital verification technologies. ‘apply to any other device,’ he said, but analog verification struggled to keep up.

What he wanted to achieve with Symphony was the ability to combine the company’s cutting-edge AFS technology with any digital simulator on the market, from Cadence’s Xcelium to Siemens EDA’s Questa.

It was designed to address many of the limitations engineers face when verifying mixed-signal designs. Siemens hopes to further bridge the gap between analog and digital with Symphony Pro.

Symphony Pro brings to the analog and mixed-signal table a host of advanced digital verification tools, including the industry-standard Universal Verification Methodology (UVM), which provides rapid simulation in a unified environment for throughput and higher capacity. The fact that it can support Unified Power Format (UPF) means engineers can also check chip designs through the lens of power consumption.

There are trade-offs, however. Symphony Pro is only compatible with numerical solvers from Siemens EDA.

visual learning

Debugging is one part of the verification process that remains a challenge when it comes to mixed signals. The complexities of mixed-signal ICs mean that engineers must painstakingly hand-scan through tons of waveforms, schematics, and other data to find problems. So, they have to rely on knowledge, intuition, and lots of trial and error to figure out what’s wrong with IC designs that refuse to cooperate.

To reduce the time needed to find and fix bugs, Symphony Pro comes with a debugging environment called Visualizer MS. It promises to save engineers a lot of headaches by providing more extensive analysis and automation capabilities.

What sets Symphony Pro apart from other software tools on the market is that it creates an abstract representation of a chip design and then generates a database of virtually everything you need to know about it. This includes digital block information – in the form of Verilog and SystemVerilog – and analog block details down to the transistor level, as well as analog and digital waveforms.

The software feeds all information into the Visualizer MS Debug environment, which opens several windows that allow engineers to easily navigate and examine a design from different points of view.

“You get a very comprehensive view of your mixed-signal design,” Vishwakarma said, making it easier to identify weak points in designs, reducing the time needed to resolve defects.

Included are the “Design Window”, which shows the full mixed-signal hierarchy, with color coding for different simulation languages, and the “Source Window” which shows the source code for different blocks in Spice and HDL. Other windows show the underlying schematics of the transistors and the many boundary connections between analog and digital blocks, where problems tend to accumulate.

One of its most advanced bug detection features is called “Logic Cone,” which digs into the vast amounts of simulation data to locate the source or “driver” of a specific problem in a design, said Vishwakarma.

One of the first customers of the Symphony Pro platform is Silicon Labs. The company has used the software to reduce the time it takes to verify its chips for the IoT market from days to hours.

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