Breker Verification Systems Joins RISC-V International as a Strategic Member to Drive Cache Consistency and SoC Integration Verification Methodologies – EEJournal

Leverage de-facto standard cache-integration and consistency testing solutions for rigorous, commercial-grade RISC-V verification

SAN JOSE, CA. –– June 11, 2022 –– Circuit Breaker Verification Systemsthe leading provider of advanced test content synthesis solutions, including RISC-V Cache Coherency and other SoC Verification Intellectual Property (VIP) integrations in the “TrekApps” family, today joined RISC-V International (RVI ) as a strategic member.

Breker will offer its expertise in SoC verification solutions to IVR workgroups.

“As the complexity of RISC-V processors for edge systems continues to increase, rigorous commercial verification has become paramount,” notes Calista Redmond, CEO of RISC-V International, the nonprofit organization that maintains RISC-V as a free and open processor instruction set architecture (ISA). “Breker’s proven expertise and knowledge in this area is invaluable in enabling the industry to meet these challenges.”

Breker is known for his leadership in test content synthesis that leverages C++ and the Accellera Portable Stimulus Standard (PSS) specification models for UVM and SoC applications. It provides a portfolio of TrekApps that generates optimized high-coverage tests to address common verification scenarios, including cache coherency, security, power domain management, packet generation, and ARM processor integration and RISC-V. Breker’s portfolio, used by many leading semiconductor companies, is directly applicable to RISC-V SoCs and invaluable to both processor developers looking for quality and end users looking to increase the confidence in integrated devices.

“RISC-V International revolutionized the semiconductor industry, and we are now seeing the result in widespread industrial activity and with many of our semiconductor customers,” notes David Kelf, CEO of Breker. “Rigorous business verification is now critical to the continued success of RISC-V and Breker is committed to working with the organization to deliver such solutions.”

Breker joined to influence the development of a consistency testing and cache integration content platform for RISC-V processor development and end-use verification. With the RISC-V ISA leveraged in more advanced application processors, this type of platform provides essential test functionality for many RISC-V players.

Breker at the Design Automation conference

Breker will showcase its System Consistency Synthesis TrekApp and other solutions at Design Automation Conference (DAC) at Booth #2528 (Second Floor) Monday, July 11 through Wednesday, July 13, 10:00 a.m. to 6:00 p.m., Moscone West, San Francisco.

Send an e-mail to [email protected] to organize a meeting or a demonstration.

About Breker Verification Systems

Circuit Breaker Verification Systems is a leading provider of Portable Stimulus solutions, a standard way to specify verification intent and reusable behaviors across target platforms. It is the first company to introduce graph-based verification and synthesis of powerful test sets from intent-based abstract scenario models based on AI scheduling algorithms. Breker’s Test Suite Synthesis and TrekApp library enables automated generation of powerful, high-coverage test cases for deployment in a variety of UVM, SoC, and Post-Silicon verification environments. Case studies featuring Altera (now Intel), Analog Devices, Broadcom, IBM, Huawei and other companies using Breker’s solutions are available at Breker’s website. Breker is privately held and works with major semiconductor companies around the world.