Reducing power consumption is essential for mobile applications and data centers. Still, it’s a challenge to reduce horsepower while having minimal impact on performance. The solution was to partition the designs into multiple power domains that selectively reduce voltage levels or power down partitions.
The traditional low power check only validates the functional correctness of the power control logic, it does not validate the impact of the power logic on the multi-clock logic.
Solving these clock domain crossover (CDC) problems requires new power-sensitive CDC analysis techniques:
- Low power consumption clock and reset analysis
- Identification of low power CDC paths and synchronization structures
- Identifying and Debugging Low Power CDC Violations
These low-power design and verification methodologies and techniques are supported by refinement features in the IEEE 1801 Unified Power Format (UPF) and by the advanced capabilities of the Questa CDC and Questa Power- verification tools. Aware, both from Siemens EDA, part of Siemens Digital Industries Software. The latest UPF standards allow designers to begin the design and verification of power distribution networks earlier in the design flow and continue to refine power systems throughout the design cycle. It is essential that designers begin CDC verification for power distribution networks at RTL level.
This low power CDC check flow is an incremental change from the traditional CDC RTL check flow. In the traditional flow, low power elements are added to the design during the implementation phase of the project, so the low power CDC analysis will occur late in the design project. For Power Aware CDC verification, the power annotation adds the low power elements specified in the UPF to the RTL design.
Fig. 1: Power sensitive CDC check flow.
The low-power CDC scan flow typically follows these five steps:
- Generate a parameterized UPF
- Compile the RTL design
- Run CDC scan with UPF
- Generate a power sensitive CDC report
Apply the methodology
For traditional designs, static structural analysis is used to identify correct and incorrect CDC timing structures. For low power designs, isolation and retention cells should be examined to ensure that incorrect CDC paths are correct, as these cells should not disrupt correct CDC structures and should not introduce new CDC paths. .
Advanced low-power designs take advantage of common CDC verification techniques to ensure that data transfer between power domains is not corrupted by metastability. These CDC verification techniques include identifying CDC paths and low power synchronization structures as well as support for isolation and retention cells. Static structural analysis is a typical technique used to verify CDC paths, but for low power designs, isolation and retention cells should be examined to ensure that incorrect CDC paths are identified and corrected.
Using power-sensitive CDC analysis, designers are able to identify CDC paths affected by low-power structures. Designers must ensure that the isolation signals are properly synchronized on the CDC paths. Figure 2 shows both data activation and isolation sources in the same clock domain as the destination register.
Fig. 2: Activation of isolation on the correct clock domain.
In addition, CDC analysis should detect scenarios where the isolation signals are not properly synchronized. In Figure 3, there is no CDC crossover on path B1-B2 which is shown in the RTL, but CDC B3-B2 crossover is introduced with UPF. When the isolation activation is in the clk2 domain is asserted or de-asserted, it can generate an asynchronous event that would lead to metastability on the B2 register in the clk1 domain. Designers can also use power-sensitive CDC verification to validate the correct use of retention cells.
Fig. 3: Activation of isolation on an incorrect clock domain.
Power sensitive CDC analysis detects cases where low power logic introduces combinational logic into the fan-in of a synchronizer. In Figure 4, a 2DFF synchronizer structure is correctly implemented in RTL from B1 to B2 synchronizer, but the isolation cell is described by the UPF and the isolation logic creates a combinatorial logic violation. Fanin combinatorial logic in synchronization structures will reduce the reliability of the synchronizer. As with CDC combinatorial logic violations, designers should ensure that design logic must first be saved before driving a CDC synchronizer.
Fig. 4: The isolation logic introduces a combinatorial logic violation.
To signal CDC results, CDC paths related to low power logic are flagged as separate diagrams, as shown in these examples of power sensitive CDC diagrams.
UPF adds combinatorial logic to a crossover.
The UPF isolation cell activation signal does not have a suitable synchronizer.
The UPF retention registry restore port does not have an appropriate synchronizer.
The specific low power diagrams allow engineers to distinguish between non-power CDC paths and CDC paths affected by low power logic. For teams focused on low power issues, the separate diagrams make it easy for them to identify, investigate, and debug low power CDC issues.
The successive refinement features in IEEE 1801 allow designers to begin the design and verification of power distribution networks earlier in the design flow and continue to refine power networks throughout the design cycle. It is essential that designers begin CDC verification for power distribution networks at RTL level. Power Sensitive CDC Analysis allows design teams to start CDC analysis before low power logic is added to the design during implementation and avoids detection of CDC errors late in the stream design at the door.
Power management continues to be a critical need for IoT and mobile designs. With the advancement of low power design, low power design and verification methodologies and techniques continue to evolve. For a more in-depth treatment of the effects of advanced low power design on CDC design and verification, especially CDC issues caused by adding power control logic, including isolation cells, retention cells and level shifters you can read the new Siemens EDA white paper Did Power management interrupts my CDC logic? The article also describes how to use this feed on an actual design and shares the results.
Kurt Takara is a Product Engineer at Siemens EDA and specializes in assertion-based verification methods and applications, including formal verification and Clock Domain Crossover (CDC) verification. He has over 20 years of experience in technical design and verification, technical marketing and engineering services. Takara has held engineering, marketing, consulting and project management roles at electronics and EDA companies such as Synopsys, Ikos Systems, Raytheon and Magnavox. He holds a BSEE from Purdue University and an MBA from Santa Clara University.